The present invention relates to a flash memory device and a fabrication method thereof and, more particularly, to a flash memory device wherein an interference phenomenon between floating gates can be improved, and a fabrication method thereof.
A flash memory device is comprised of a floating gate for storing data and a control gate for program, erase and read operations. Specifically, a flash memory device has a structure in which a tunnel insulating film, a floating gate, a dielectric layer and a control gate are laminated over a semiconductor substrate. The tunnel insulating film is generally formed of an oxide film and functions to prohibit electrons, stored in the floating gate, from being drained to the semiconductor substrate. The dielectric layer is formed between the floating gate and the control gate and functions to prohibit electrons, stored in the floating gate, from being drained to the control gate. A capacitance value may be changed depending on the dielectric constant of the dielectric layer. As the capacitance value varies, the coupling ratio is changed.
This flash memory device is a kind of device in which data stored therein is retained even if power is off, and has been in the spotlight as portable devices. In order to realize portability and a large capacity, the flash memory device is gradually miniaturized. To this end, the level of integration of devices has gradually increased.
As devices are highly integrated, a distance between the floating gates is narrowed and accordingly, a high dielectric (high-k) material is used as the dielectric layer. In this case, however, parasitic capacitance between memory cells may be increased due to an increase of the dielectric constant. Due to this, an interference phenomenon between the memory cells is increased, so reliability of devices may be lowered.